This present invention relates to the field of electronic design automation for electronic circuits, and more specifically, to systems and techniques to solve a network using a Barycenter compact model and a hierarchical scheduler.
The age of information and electronic commerce has been made possible by the development of electronic circuits and their miniaturization through integrated circuit technology. Integrated circuits are sometimes referred to as “chips.” Some types of integrated circuits include digital signal processors (DSPs), amplifiers, dynamic random access memories (DRAMs), static random access memories (SRAMs), erasable programmable read only memories (EPROMs), electrically erasable programmable read only memories (EEPROMs), Flash memories, microprocessors, application specific integrated circuits (ASICs), and programmable logic
Integrated circuits have been widely adopted and are used in many products in the areas of computers and other programmed machines, consumer electronics, telecommunications and networking equipment, wireless network and communications, industrial automation, and medical instruments, just to name a few. Electronic circuits and integrated circuits are the foundation of the Internet and other on-line technologies including the World Wide Web (WWW).
There is a continuing demand for electronic products that are easier to use, more accessible to greater numbers of users, provide more features, and generally address the needs of consumers and customers. Integrated circuit technology continues to advance rapidly. With new advances in technology, more of these needs are addressed. Furthermore, new advances may also bring about fundamental changes in technology that profoundly impact and greatly enhance the products of the future.
To meet the challenges of building more complex and higher performance integrated circuits, software tools are used. These tools are in an area commonly referred to as computer aided design (CAD), computer aided engineering (CAE), or electronic design automation (EDA). There is a constant need to improve these electronic automatic tools in order to address the desire for higher integration and greater complexity, and better performance in integrated circuits.
Large modern day integrated circuits have millions of devices including gates and transistors and are very complex. As process technology improves, more and more devices may be fabricated on a single integrated circuit, so integrated circuits will continue to become even more complex with time. In the past, many parasitic effects may not have been considered because they were less significant or insignificant compared to other factors.
As lithography and miniaturization techniques advance, on-chip devices and line widths become smaller, frequencies increase. As a consequence, many more impedances such as parasitic resistances, inductances, and capacitances and parasitic effects need to be considered. If these parasitics and effects are not taken into account, poor simulation results will result, and possible the electronic circuits will not work as expected after the circuit is fabricated. As more and more parasitic and other effects are accounted for, the circuit networks to be simulated become much more complex. As complexity increases, simulating the network takes significantly more computing resources and computation time.
More specifically, in nanometer, gigahertz, low power VLSI design, power, and signal integrity has become critical. To accurately analyze chip performance, it is desirable to consider the impact of power fluctuation, and the capacitive, inductive, or even substrate coupling noise with devices, or any combination of these. This analysis entails considering a very large amount of elements, which results in a very large system matrix for circuit simulation. This is a lack of a circuit simulation algorithm that can simultaneously resolve a large number of linear or linear with nonlinear devices while maintaining both efficiently and accuracy.
Some problems with the prior art are performance, capacity (millions of elements), accuracy (iterative matrix solver may be divergent for large network and hard for parallel processing and distributed computing), the size of memory has limitation in the computer, multi-thread is limited by memory size, distributed computing (does not share memory), diakoptics (tearing and reassembly, but no reassembly method for hierarchical design), and no efficient way to formulate the hierarchical boundary condition and solve the problem.
Therefore, there is a need for tools for solving networks.